1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device in which transistors whose application voltages are different from each other are provided in a mixed manner.
2. Description of Related Art
For a related-art CMIS transistor, polysilicon (poly-Si) is generally used as its gate electrode. The current drive capability Ids of the CMIS transistor is represented by Equation (1) in general.
                              I          on                =                              I            ds                    =                                    μ              eff                        ×                          C              ox                        ×                          W              L                        ×                                                            (                                                            V                      g                                        -                                          V                      th                                                        )                                2                                            2                ⁢                m                                                                        (        1        )            
Actually the capacitance of polysilicon as the gate material is also included in the capacitance Cox of the gate insulating film. This lowers the current drive capability Ids, which results in a long circuit delay time T as shown in Equation (2).
                    τ        =                              CV            I                    =                                    (                                                C                  Tr                                +                                  C                  Mtl                                            )                        ⁢                                          V                dd                                            I                on                                                                        (        2        )            
Because of this background, a metal gate, in which no depletion layer is generated, is used as the gate. For example, for a high-speed, low-power-consumption MIS transistor, studies are being made about use of a gate stack structure composed of a gate insulating film having a dielectric constant higher than that of silicon oxide and a metal gate (hereinafter, referred to as “high dielectric constant film/metal gate”). However, in a normal manufacturing method, the thermal history after the formation of the high dielectric constant film/metal gate includes high temperatures, which leads to problems of the deterioration of the characteristics and reliability of the high dielectric constant insulating film and the shift of the work function of the metal gate from the design value.
To avoid these problems, a buried gate (e.g. damascene gate) structure obtained through the completion of the major heat treatment steps necessary to form the transistor before the formation of the high dielectric constant film/metal gate has been proposed (refer to e.g. Japanese Patent Laid-open No. 2001-102443). For example, if a metal electrode is used, this structure is obtained by a method in which initially a transistor structure is formed by using a silicon oxide gate insulating film and a polysilicon gate electrode, and thereafter the gate insulating film and the gate electrode part are removed and then a metal oxide film and a metal electrode are newly buried. In this method, the heat treatment necessary to form the transistor is completed before the formation of the metal electrode, and therefore the deterioration of the metal electrode does not occur.
Another method has also been proposed. In this method, in order to prevent a polysilicon gate electrode from being polished at the time of metal polishing by chemical mechanical polishing (CMP), the height of a damascene gate electrode for high-speed and low-voltage operation is set larger than that of the polysilicon gate electrode for high-breakdown-voltage operation at the timing when the damascene gate is processed (refer to e.g. Japanese Patent Laid-open No. 2004-6475).
However, an actual semiconductor device includes both a transistor that is required to operate at high speed/low power consumption and employs a metal oxide film and a metal electrode and a transistor that operates with high voltage and employs a related-art silicon oxide gate insulating film and a related-art polysilicon gate electrode. Therefore, on the same chip, a damascene gate structure having high dielectric constant film/metal gate for high-speed and low-voltage operation and a gate structure having a thicker gate insulating film for high-breakdown-voltage operation need to be formed on the same substrate in a mixed manner.
With reference to the manufacturing-step sectional views of FIGS. 4A to 4M, a description will be made below about one example of a method for manufacturing a semiconductor device that includes both a transistor that is obtained through the completion of the heat treatment necessary to form the transistor before formation of a metal electrode and employs a metal oxide film and the metal electrode and a transistor that operates with high voltage and employs a related-art silicon oxide gate insulating film and a related-art polysilicon gate electrode.
Referring to FIG. 4A, element isolation regions 12 that isolate areas LVN-1, LVN-2, LVP, MV, and HV from each other are formed in a semiconductor substrate 11 by carrying out an element isolation step. In the areas LVN-1, LVN-2, and LVP, low-voltage transistors (e.g. MISFETs) are to be formed. In the area MV, a middle-voltage transistor (e.g. MISFET) is to be formed. In the area HV, a high-voltage transistor (e.g. MISFET) is to be formed. The areas MV and HV include both an area in which the MISFET pattern density will be high and an area that will have an isolated MISFET pattern. The area HV, in which the high-voltage transistor is to be formed, and the area MV, in which the middle-voltage transistor is to be formed, are defined as a first area 11A. The area LVN-1, in which NMISFETs as the low-voltage transistors are to be formed with high density, the area LVN-2, in which an NMISFET as the low-voltage transistor is to be formed in an isolated manner, and the area LVP, in which a PMISFET as the low-voltage transistor is to be formed, are defined as a second area 11B.
Subsequently, ion implantation for forming P-well regions (not shown) in the areas in which the NMISFETs are to be formed, ion implantation for forming buried layers (not shown) for preventing punch-through of the MISFETs, and ion implantation for adjusting the threshold voltage (Vth) are adequately performed, to thereby form NMIS channel regions. In addition, ion implantation for forming N-well regions (not shown) in the areas in which the PMISFETs are to be formed, ion implantation for forming buried layers (not shown) for preventing punch-through of the MISFETs, and ion implantation for adjusting the threshold voltage (Vth) are adequately performed, to thereby form PMIS channel regions. The ion implantation may be performed with different ion implantation conditions that each correspond to a respective one of the area HV, in which the high-voltage transistor is to be formed, the area MV, in which the middle-voltage transistor is to be formed, and the areas LVN-1, LVN-2, and LVP, in which the respective low-voltage transistors are to be formed.
Subsequently, a gate insulating film 13 is formed on the surfaces of the area HV and the area MV of the semiconductor substrate 11. The high-voltage transistor and the middle-voltage transistor frequently have a thick gate insulating film, and the gate insulating film 13 is formed by using e.g. a silicon oxide film. This silicon oxide film is formed by e.g. thermal oxidation at a temperature in the range of 750° C. to 900° C., and the thickness thereof is in the range of 2 nm to 4 nm. In the formation of the gate insulating film 13, the gate insulating film 13 is formed also above the active regions in the second area 11B simultaneously. This gate insulating film 13 in the second area 11B is used as a dummy gate insulating film 14.
Subsequently, a gate forming step is carried out. Initially, an electrode forming film for forming first gate electrodes and dummy gate electrodes is formed on the gate insulating film 13 and the dummy gate insulating film 14. This electrode forming film is formed by depositing e.g. polysilicon or amorphous silicon over the entire surface with the intermediary of the gate insulating film 13 and the dummy gate insulating film 14 on the semiconductor substrate 11. For example, if the electrode forming film is formed by using polysilicon, low-pressure CVD in which e.g. monosilane (SiH4) is the source gas and the deposition temperature is in the range of 580° C. to 620° C. is used to deposit polysilicon to a thickness in the range of 100 nm to 150 nm. Subsequently, an ion implantation step for reducing the gate resistance is carried out for the partial portion of the electrode forming film in the first area 11A.
Subsequently, a hard mask layer is formed on the electrode forming film. This hard mask layer is formed by depositing silicon nitride (SiN) to a thickness in the range of e.g. 50 nm to 100 nm by e.g. low-pressure CVD (LP-CVD).
Subsequently, a resist pattern (not shown) for forming the first gate electrodes and the dummy gate electrodes is formed over the electrode forming film by resist coating and a lithography technique, and then the hard mask layer is processed by e.g. anisotropic etching with use of the resist pattern as the etching mask. Thereby, hard masks 74A for forming first gate electrodes 15 of the high-voltage transistor and the middle-voltage transistor in the first area 11A, and hard masks 74B for forming second gate electrodes of the low-voltage transistors in the second area 11B are formed. In this anisotropic etching, a gas based on e.g. hydrogen bromide (HBr) or chlorine (Cl) is used as the etching gas. Furthermore, by using the hard masks 74A and 74B as an etching mask, the first gate electrodes 15 are formed in the first area 11A, and simultaneously dummy gate electrodes 16 are formed in the second area 11B. At this time, the gate insulating film 13 and the dummy gate insulating film 14 are also etched.
Subsequently, an insulating film for forming offset spacers is so formed over the semiconductor substrate 11 by e.g. low-pressure CVD as to cover gate parts 17 composed of the hard masks 74A, the first gate electrodes 15, and the gate insulating film 13 and dummy gate parts 18 composed of the hard masks 74B, the dummy gate electrodes 16, and the dummy gate insulating film 14. This insulating film is formed by using a silicon nitride film by e.g. low-pressure CVD. Subsequently, the offset spacers (not shown) are formed by etching back the insulating film for the entire surface. The thickness of the silicon nitride film deposited by low-pressure CVD is in the range of e.g. 6 nm to 10 nm.
Subsequently, an ion implantation mask (not shown) is formed over the semiconductor substrate 11 in the second area 11B. This ion implantation mask is formed e.g. by forming a resist film across the entire surface by a resist coating technique and then processing the resist film by a lithography technique in such a way that the first area 11A is exposed and the second area 11B is covered. Subsequently, ion implantation into the semiconductor substrate 11 is performed with use of this resist film as the ion implantation mask, to thereby form extension regions 21 and 22 in the vicinity of the surface of the semiconductor substrate 11 and on the sides of the respective gate parts 17 in the first area 11A. If there is a need to fabricate both an NMISFET and a PMISFET in the first area 11A, different ion implantation masks that each correspond to a respective one of the NMISFET area and the PMISFET area are separately formed and different kinds of ion implantation that each correspond to a respective one of the MISFETs are carried out. After the ion implantation, the ion implantation mask is removed.
Subsequently, another ion implantation mask (not shown) is formed over the semiconductor substrate 11. This ion implantation mask is formed e.g. by forming a resist film across the entire surface by a resist coating technique and then processing the resist film by a lithography technique in such a way that the areas LVN-1 and LVN-2 of the second area 11B are exposed and the first area 11A and the area LVP are covered. Ion implantation into the semiconductor substrate 11 is performed with use of this ion implantation mask (not shown), to thereby form extension regions 23 and 24 of the NMISFETs in the vicinity of the surface of the semiconductor substrate 11 and on the sides of the respective dummy gate parts 18 in the areas LVN-1 and LVN-2. Thereafter, the ion implantation mask is removed.
Subsequently, yet another ion implantation mask (not shown) is formed over the semiconductor substrate 11. This ion implantation mask is formed e.g. by forming a resist film across the entire surface by a resist coating technique and then processing the resist film by a lithography technique in such a way that the area LVP is exposed and the areas LVN-1 and LVN-2 of the second area 11B and the first area 11A are covered. Ion implantation into the semiconductor substrate 11 is performed with use of this ion implantation mask, to thereby form extension regions 25 and 26 of the PMISFET in the vicinity of the surface of the semiconductor substrate 11 and on the sides of the dummy gate part 18 in the area LVP. Thereafter, the ion implantation mask is removed.
In the above-described respective ion implantation steps, the gate parts 17, the dummy gate parts 18, and the offset spacers (not shown) also serve as the ion implantation mask. In this manner, both the NMISFETs and the PMISFET are fabricated in the second area 11B. The order of the formation of the extension regions 21 and 22, the extension regions 23 and 24, and the extension regions 25 and 26 may be any order.
Subsequently, an insulating film for forming sidewalls is so formed over the semiconductor substrate 11 by e.g. low-pressure CVD as to cover the gate parts 17, the dummy gate parts 18, and the offset spacers (not shown). This insulating film is formed by low-pressure CVD by using e.g. a multilayer film composed of a silicon nitride film (with a thickness in the range of e.g. 15 nm to 30 nm) and a TEOS (Tetra Ethyl Ortho Silicate) film (with a thickness in the range of e.g. 40 nm to 60 nm). Subsequently, sidewalls 20 are formed by etching back the insulating film for the entire surface.
Subsequently, sources/drains are formed. Specifically, an ion implantation mask (not shown) is formed over the semiconductor substrate 11 in the second area 11B. This ion implantation mask is formed e.g. by forming a resist film across the entire surface by a resist coating technique and then processing the resist film by a lithography technique in such a way that the first area 11A is exposed and the second area 11B is covered. Subsequently, ion implantation into the semiconductor substrate 11 is performed with use of this resist film as the ion implantation mask, to thereby form source/drain regions 27 and 28 in the vicinity of the surface of the semiconductor substrate 11 and on the sides of the respective gate parts 17 in the first area 11A, with the intermediary of the extension regions 21 and 22 between the source/drain regions 27 and 28. In this ion implantation, the gate parts 17 and the sidewalls 20 (including the offset spacers) also serve as the ion implantation mask. After the ion implantation, the ion implantation mask is removed.
Similarly, another ion implantation mask (not shown) is formed over the semiconductor substrate 11 in the first area 11A and the area LVP of the second area 11B. This ion implantation mask is formed e.g. by forming a resist film across the entire surface by a resist coating technique and then processing the resist film by a lithography technique in such a way that the areas LVN-1 and LVN-2 of the second area 11B are exposed and the first area 11A and the area LVP of the second area 11B are covered. Subsequently, ion implantation into the semiconductor substrate 11 is performed with use of this resist film as the ion implantation mask, to thereby form source/drain regions 29 and 30 in the vicinity of the surface of the semiconductor substrate 11 and on the sides of the respective dummy gate parts 18 in the areas LVN-1 and LVN-2 of the second area 11B, with the intermediary of the extension regions 23 and 24 between the source/drain regions 29 and 30. In this ion implantation, the dummy gate parts 18 and the sidewalls 20 (including the offset spacers) also serve as the ion implantation mask. After the ion implantation, the ion implantation mask is removed.
Similarly, yet another ion implantation mask (not shown) is formed over the semiconductor substrate 11 in the first area 11A and the areas LVN-1 and LVN-2 of the second area 11B. This ion implantation mask is formed e.g. by forming a resist film across the entire surface by a resist coating technique and then processing the resist film by a lithography technique in such a way that the area LVP of the second area 11B is exposed and the first area 11A and the areas LVN-1 and LVN-2 of the second area 11B are covered. Subsequently, ion implantation into the semiconductor substrate 11 is performed with use of this resist film as the ion implantation mask, to thereby form source/drain regions 31 and 32 in the vicinity of the surface of the semiconductor substrate 11 and on the sides of the dummy gate part 18 in the area LVP of the second area 11B, with the intermediary of the extension regions 25 and 26 between the source/drain regions 31 and 32. In this ion implantation, the dummy gate part 18 and the sidewalls 20 (including the offset spacers) also serve as the ion implantation mask. After the ion implantation, the ion implantation mask is removed.
In this manner, both the NMISFETs and the PMISFET are fabricated in the second area 11B. The order of the above-described ion implantation steps is not limited to the above-described order, but any of the source/drain regions 27 and 28 in the first area, the source/drain regions 29 and 30 in the areas LVN-1 and LVN-2, and the source/drain regions 31 and 32 in the area LVP may be formed first or last.
Subsequently, the TEOS portion of the sidewalls 20 is removed. For this removal, e.g. wet etching with a diluted hydrofluoric acid is used. Thereafter, heat treatment for activating the implanted ions is performed. For example, by this heat treatment, the impurities are activated under a condition of 1000° C. and five seconds, so that the source/drain regions 27 to 32 of the respective MISFETs are formed. It is also possible to perform the heat treatment by spike RTA for the purpose of promoting the dopant activation and suppressing diffusion.
Subsequently, a silicide layer 33 is formed on the respective source/drain regions 27 to 32. Initially, a metal layer for forming silicide is formed over the entire surface. In the present example, cobalt (Co) is used for the metal layer as one example. The metal layer is formed by deposing cobalt to a thickness in the range of e.g. 6 nm to 8 nm by e.g. sputtering. Subsequently, RTA is performed at a temperature in the range of 500° C. to 600° C. to thereby form the silicide layer 33 through the reaction of only the metal layer on silicon (Si) of the semiconductor substrate 11. Because the metal layer is composed of cobalt, the silicide layer 33 is obtained as a cobalt silicide (e.g. CoSi) layer. Thereafter, the unreacted cobalt on the insulating films (e.g. the element isolation regions 12, the hard masks 74A and 74B, and the sidewalls 20) is removed by wet etching with a mixed liquid of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Subsequently, heat treatment is performed to form lower-resistance cobalt silicide (CoSi2). This heat treatment is performed by e.g. RTA at a temperature in the range of 650° C. to 850° C. for 30 seconds. It is also possible that nickel (Ni) or nickel-platinum (NiPt) is used for the metal layer instead of cobalt (Co) to thereby form nickel silicide (NiSi2). In any case, the RTA temperature can be adequately set.
Subsequently, an insulating film is formed to cover the gate parts 17, the dummy gate parts 18, and so on. As the insulating film, initially a liner film 36 is formed over the entire surface of the semiconductor substrate 11. This liner film 36 is formed of e.g. a silicon nitride (SiN) film, and applies stress on the channel parts of the transistors. For example, for an NMISFET, a film applying tensile stress is used in order to enhance the channel mobility. For a PMISFET, a film applying compressive stress is used in order to enhance the channel mobility. The different liner films 36 may be fabricated for the NMISFETs and the PMISFET. The stress of the liner film 36 can be determined depending on the film deposition condition in general.
Referring next to FIG. 4B, a first interlayer insulating film 38 as a part of the insulating film is formed on the liner film 36. This first interlayer insulating film 38 is formed e.g. by using a silicon oxide (SiO2) film having a thickness in the range of 100 nm to 200 nm by high density plasma (HDP) CVD.
Subsequently, as shown in FIG. 4C, the first interlayer insulating film 38 and the liner film 36 over the gate parts 17 and the dummy gate parts 18 are polished by chemical mechanical polishing (CMP) until the respective hard masks 74A and 74B are exposed.
Subsequently, as shown in FIG. 4D, an etching mask 75 that covers the second area 11B is formed by a resist coating technique and a lithography technique. The hard masks 74A (see FIG. 4C) in the first area 11A are removed with use of this etching mask 75 to thereby expose the upper surfaces of the first gate electrodes 15. At this time, upper parts of the first interlayer insulating film 38 and the liner film 36 are also removed by etching. Thereafter, the etching mask 75 is removed. FIG. 4D shows the state before the etching mask 75 is removed.
Subsequently, as shown in FIG. 4E, a silicide layer 40 is formed on the respective first gate electrodes 15. Initially, a metal layer for forming silicide is formed over the entire surface. In the present example, cobalt (Co) is used for the metal layer as one example. The metal layer is formed by deposing cobalt to a thickness in the range of e.g. 6 nm to 8 nm by e.g. sputtering. Subsequently, RTA is performed at a temperature in the range of 500° C. to 600° C. to thereby form the silicide layer 40 through the reaction of only the metal layer on silicon (Si) of the first gate electrodes 15. Because the metal layer is composed of cobalt, the silicide layer 40 is obtained as a cobalt silicide (e.g. CoSi) layer. Thereafter, the unreacted cobalt on the insulating films (e.g. the sidewalls 20, the liner film 36, the first interlayer insulating film 38, and the hard masks 74B) is removed by wet etching with a mixed liquid of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Subsequently, heat treatment is performed to form lower-resistance cobalt silicide (CoSi2). This heat treatment is performed by e.g. RTA at a temperature in the range of 650° C. to 850° C. for 30 seconds. It is also possible that nickel (Ni) or nickel-platinum (NiPt) is used for the metal layer instead of cobalt (Co) to thereby form nickel silicide (NiSi2). In any case, the RTA temperature can be adequately set.
Subsequently, as shown in FIG. 4F, a protective film 41 for protecting the silicide layer 40 is formed over the entire surface. This protective film 41 is formed e.g. by using a silicon oxide (SiO2) or silicon nitride (SiN) film by plasma CVD. One example of the CVD condition when the protective film 41 is formed by using a silicon oxide film is as follows: oxygen (O2) (the flow rate is 600 cm3/min) and TEOS (Tetra Ethyl Ortho Silicate) (the flow rate is 800 cm3/min) are used as the source gas; the pressure of the film deposition atmosphere is 1.09 kPa; the RF power of the CVD apparatus is 700 W; and the substrate temperature is 400° C. The protective film 41 can be deposited at a temperature lower than 450° C., and thus damage to the already-formed silicide layers 33 and 40 can be avoided.
Subsequently, an etching mask 76 is so formed by resist coating and a lithography technique as to cover the first area 11A. Therefore, the second area 11B is not covered by this etching mask 76.
Subsequently, as shown in FIG. 4G, the protective film 41 (see FIG. 4F) in the second area 11B is removed by dry etching with use of the etching mask 76 (see FIG. 4F). One example of the dry etching condition is as follows: octafluorocyclobutane (C4F8), oxygen (O2), and argon (Ar) are used as the etching gas; the flow rates of C4F8, O2, and Ar are 9 cm3/min, 5 cm3/min, and 250 cm3/min, respectively; the pressure of the etching atmosphere is 4.1 Pa; the power (plasma output) of the etching apparatus is 1500 W; and the substrate temperature is 20° C. Subsequently, the hard masks 74B and the dummy gate electrodes 16 (see FIG. 4A) are removed by e.g. dry etching. Furthermore, the dummy gate insulating film 14 (see FIG. 4A) is removed by wet etching with a diluted hydrofluoric acid, so that gate forming trenches 42 are formed. At this time, the first area 11A is covered by the protective film 41. The etching mask 76 is removed before the wet etching.
Subsequently, a second gate insulating film 43 is formed on the inside surfaces of the gate forming trenches 42. This second gate insulating film 43 is so formed that the capacitance of the second gate insulating film 43 per unit area is lower than that of the first gate insulating film 13 in the first area 11A per unit area. The second gate insulating film 43 is formed by using a high dielectric constant film by atomic layer deposition (ALD). The high dielectric constant film is formed by using e.g. oxide, silicate, or oxynitride of hafnium, zirconium, lanthanum, yttrium, tantalum, or aluminum. Specifically, it is formed by using e.g. hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (LaO3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium silicate (HfSiOX), zirconium silicate (ZrSiOX), lanthanum silicate (LaSiOX), yttrium silicate (YSiOX), tantalum silicate (TaSiOX), aluminum silicate (AlSiOX), zirconium titanate (ZrTiOX), hafnium aluminum oxide (HfAlOX), or hafnium zirconium oxide (HfZrOX), or nitride of any of these compounds. In general, the relative dielectric constant of HfO2 is in the range of 25 to 30 and that of ZrO2 is in the range of 20 to 25, although the relative dielectric constant of the high dielectric constant film changes depending on the composition, the state (crystalline state or amorphous state), and so on.
Subsequently, as shown in FIGS. 4H to 4K, work function control films 44 and 45 that determine work functions are formed over the inside surfaces of the gate forming trenches 42 with the intermediary of the second gate insulating film 43.
Initially, a metal or metal compound having a work function appropriate for the NMISFETs is deposited by a film deposition method such as atomic layer deposition (ALD) or chemical vapor deposition. In general, the gate electrode of an NMISFET has a work function of 4.6 eV or lower, and preferably 4.3 eV or lower. The gate electrode of a PMISFET has a work function of 4.6 eV or higher, and preferably 4.9 eV or higher. It is desirable that the difference in the work function therebetween is equal to or larger than 0.3 eV. Specifically, the work function of HfSiX for the NMISFETs is in the range of 4.1 to 4.3 eV and that of titanium nitride (TiN) for the PMISFET is in the range of 4.5 to 5.0 eV, although changing depending on the composition, the state (crystalline state or amorphous state), and so on.
Examples of the materials of the work function control films 44 and 45 include metals such as titanium (Ti), vanadium (V), nickel (Ni), zirconium (Zn), niobium (Nb), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), and platinum (Pt), alloys containing any of these metals, and compounds of these metals. Examples of the metal compounds include metal nitrides and compounds of metal and semiconductor. One example of the compounds of metal and semiconductor is metal silicide.
Examples of the material of the work function control film 44 appropriate for the NMISFETs include metals such as hafnium (Hf) and tantalum (Ta), alloys containing any of these metals, and compounds of these metals. Specifically, hafnium silicide (HfSiX) is preferable. Examples of the material of the work function control film 45 appropriate for the PMISFET include metals such as titanium (Ti), molybdenum (Mo), and ruthenium (Ru), alloys containing any of these metals, and compounds of these metals. Specifically, titanium nitride (TiN) and ruthenium (Ru) are preferable.
In the present example, as shown in FIG. 4H, the work function control film 44 is formed by depositing e.g. hafnium silicide (HfSiX) on the surface of the second gate insulating film 43 to a thickness in the range of e.g. 10 nm to 100 nm.
Subsequently, as shown in FIG. 4I, a resist mask 77 that covers the areas LVN-1 and LVN-2 of the second area 11B is formed by resist coating and a lithography technique. The work function control film 44 in the area LVP and the first area 11A is etched by using this resist mask 77 as the etching mask. As a result, as shown in FIG. 4J, the work function control film 44 in the area LVP and the first area 11A is removed, whereas the work function control film 44 is left in the areas LVN-1 and LVN-2 of the second area 11B. Thereafter, the resist mask 77 is removed.
Subsequently, as shown in FIG. 4K, a metal or metal compound having a work function appropriate for the PMISFET is deposited by a film deposition method such as atomic layer deposition (ALD) or chemical vapor deposition. In the present example, initially the work function control film 45 is formed by depositing e.g. titanium nitride (TiN) to a thickness in the range of 5 nm to 50 nm on the surfaces of the second gate insulating film 43 and the work function control film 44. Subsequently, a resist mask (not shown) that covers the area LVP of the second area 11B is formed by resist coating and a lithography technique. The work function control film 45 in the areas LVN-1 and LVN-2 of the second area 11B and the first area 11A is etched by using this resist mask as the etching mask. As a result, the work function control film 45 in the areas LVN-1 and LVN-2 of the second area 11B and the first area 11A is removed, whereas the work function control film 45 is left in the area LVP of the second area 11B. It is also possible to deposit e.g. ruthenium (Ru) for the PMISFET. Thereafter, the resist mask is removed.
In the case of the above-described steps, it does not matter which of the work function control films 44 and 45 is formed first. If the work function control film 45 is left across the entire surface, the work function control film 44 may be formed before the formation of the work function control film 45.
Subsequently, as shown in FIG. 4L, a conductive film 46 composed of an electrically-conductive material is formed to fill the insides of the gate forming trenches 42. This conductive film 46 is formed by using e.g. a metal material whose electric resistance is lower than those of the work function control films 44 and 45. In the present example, tungsten (W) is used as one example. This tungsten film is formed through deposition by e.g. CVD. The conductive film 46 has a thickness that allows the gate forming trenches 42 to be completely filled. For example, the thickness is in the range of 200 nm to 400 nm.
Subsequently, as shown in FIG. 4M, the excess conductive film 46 (see FIG. 4L) outside the gate forming trenches 42 is removed. For this removal processing, e.g. chemical mechanical polishing (CMP) is used. In this CMP, the liner film 36, the first interlayer insulating film 38, the protective film 41, and so on serve as the polishing stopper. As a result of the CMP step, second gate electrodes 47 of the low-voltage transistors (NMISFETs) in the second area 11B are formed by the conductive film 46 and the work function control film 44 left in the gate forming trenches 42. Furthermore, a second gate electrode 48 of the low-voltage transistor (PMISFET) is formed by the conductive film 46 and the work function control film 45 left in the gate forming trench 42.
Thereafter, although not shown in the drawing, a second interlayer insulating film is formed across the entire surface over the liner film 36, the first interlayer insulating film 38, and the protective film 41, and then a wiring step is carried out.
In this way, a semiconductor device 1 is formed. In the semiconductor device 1, a middle-voltage transistor (NMISFET) 2 is formed in the area MV of the first area 11A, and a high-voltage transistor (NMISFET) 3 is formed in the area HV. Furthermore, low-voltage transistors (NMISFETs) 4 are formed with high density in the area LVN-1 of the second area 11B, and the low-voltage transistor (NMISFET) 4 is formed in an isolated manner in the area LVN-2. In addition, a low-voltage transistor (PMISFET) 5 is formed in the area LVP.
The above-described manufacturing method is very complex. Moreover, as shown in FIG. 4M, a step due to the protective film 41 is generated between the area LVP and the area MV, for example, because of the manufacturing steps. Thus, there is a high possibility that a residue of the conductive film 46 is left near the step formed at an end of the protective film 41 after the polishing of the conductive film 46. To eliminate this residue, excess polishing needs to be performed. However, if the excess polishing is performed, the second gate electrodes 47 and 48, which are metal gates, will be excessively polished. This makes it difficult to fabricate the second gate electrodes 47 and 48 in accordance with the design values. Furthermore, the excess polishing increases the degree of the surface irregularity, which makes it difficult to obtain an ideal shape, e.g., a flat shape.